(a) Field of the Invention
The present invention relates to an interconnection structure between conductors in a semiconductor device for effectively reducing contact resistance between the conductors in the interconnection structure.
(b) Description of the Related Art
In a conventional semiconductor device having various conductors overlying a semiconductor substrate, a via hole is generally formed penetrating through a dielectric film for electrically connecting a plurality of conductive layers together.
Examples of an interconnection structure between conductive layers in a conventional semiconductor device are shown in FIGS. 1A, 1B, 2A and 2B. FIG. 1A is a top plan view of an interconnection structure and FIG. 1B is a sectional view of the structure of FIG. 1A taken along a line A--A. Similarly, FIG. 2A is a top plan view of another interconnection structure and FIG. 2B is a sectional view of the structure of FIG. 2A taken along a line A--A.
As shown in FIG. 1B, a silicon oxide film 16 is formed on a semiconductor substrate 17 and first layer conductors 11 are formed on the silicon oxide film 16. A dielectric film 12 is then formed on the first layer conductors 11. After the dielectric film 12 is flattened by employing a chemical mechanical polishing (CMP) technique, a via hole 18 is formed in the dielectric film 12 for connecting the first layer conductors 11 and second layer conductor 15. The aperture size of the via hole 18 is made smaller than the area formed by overlap between the first layer conductor and the second layer conductor 11,15 as shown in FIG. 1A in order to secure the interconnection therebetween, The whole surface of the dielectric film 12 including the via hole 18 is coated with a conductive material 14 by employing a chemical vapor deposition (CVD) technique, and the top surface of the conductive material 14 is aligned with the top surface of the dielectric film 12 by employing a dry etching technique to fill the via hole 18 with the conductive material 14 to make the via plug. After this procedure, the second layer conductor 15 is formed on the via plug 18.
As shown in FIG. 2B, a silicon oxide film 26 is formed on a semiconductor substrate 27 and two first layer conductors 21 are separately formed on the silicon oxide film 26. A dielectric film 22 is then formed on the first layer conductors 21 and on the silicon oxide film 26. Via holes 28 are formed smaller than an area formed by overlap between the first layer conductor 21 and a second layer conductor 25. The via holes 28 are filled with a conductive material 24 and the second layer conductor 25 is formed on the via plugs 28 and the dielectric film 22.
The width of conductors is generally made smaller and smaller in order to decrease the parasitic capacitance of the conductors for responding to a recent demand of high operational speed. Since the above decrease makes, an area formed by overlap between the first layer conductor and the second layer conductor smaller to reduce the aperture area, a contact resistance between the first layer conductor and the conductive material filled in the via hole increases. When a barrier metal layer is formed in the via hole by means of sputtering, a thickness of the barrier metal layer,at the bottom of the via hole is thinner than desired because the aperture area of the via hole is small so that the scattering of the contact resistance between the barrier metal layer in the via plug and the first layer conductor becomes larger. Since, further, the via hole is smaller than an area formed by overlapping between the first and the second layer conductors, the high accuracy of position adjustment between a mask for forming the via hole and the first layer conductor is required.
In order to solve this problem, a structure shown in FIGS. 3A to 3C is proposed (JP-A-09(1997)-17868). FIG. 3A is a top plan view of the structure, and FIGS. 3B and 3C, are sectional views taken along the lines A--A and B--B, respectively, of FIG. 3A.
As shown in FIG. 3B, a silicon oxide film 36 is formed on a semiconductor substrate 37 and a first layer conductor 31 is formed on the central part of the silicon oxide film 36. A dielectric film 32 is then formed on the first layer conductor 31 and on the silicon oxide film 36. A via hole 39 is formed in the dielectric film 32 for connecting the first layer conductor 31 and a second layer conductor 35. This via hole 39 is made larger than an area formed by overlapping between the first and the second layer conductors 31, 35 as shown in FIG. 3A. The second layer conductor 35 is so formed that it is in contact with the first layer conductor 31 through the via hole 39.
However, in this interconnection structure between the conductors, an unnecessary trench is formed between the dielectric film 32 and the second layer conductor 35 as shown in FIG. 3C so that coverage of the upper layers becomes worse. When two or more first layer conductors are present as shown in FIG. 2B, the same number of via holes as that of the first layer conductors are required. If the via hole shown in FIG. 3B is formed in FIG. 2B, further unnecessary trenches are produced.